8-bit RISC based CPU

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8-bit RISC based CPU af Mind Map: 8-bit RISC based CPU

1. Instruction Decoder

1.1. FETCH/INCREMENT

1.2. ALU

1.2.1. SETAB

1.2.2. MOV_ALU_IN

1.2.3. ALU

1.2.4. MOV_ALU_OUT

1.3. MOV

1.3.1. MOV

1.3.2. MOV16

1.4. Memory Access

1.4.1. LOAD

1.4.2. STORE

1.5. Flags

1.5.1. STORE_FLAGS

1.5.2. LOAD_FLAGS

1.5.3. SAVE_FLAGS

1.5.4. RESTORE_FLAGS

1.5.5. FLAGS_TO_OUTBUFFER

1.5.6. INBUFFER_TO_FLAGS

1.6. Jumps

1.6.1. JMP

1.6.2. JZ

1.6.3. JNS

1.6.4. JNC

1.6.5. JNZ

1.6.6. 16BIT_ADDER

1.7. IO

1.7.1. IN

1.7.2. OUT

1.8. HLT

2. General Purpose Registers

2.1. 8-bit Register

2.1.1. D

2.1.2. E

2.1.3. F

2.1.4. G

2.1.5. H

2.1.6. XL

2.1.7. XH

2.1.8. XE

2.2. 16-bit Register

2.2.1. M

2.2.2. X

2.2.3. J

2.2.4. SP

2.2.5. BP

2.2.6. PC

2.2.7. INC

2.2.8. Y

2.2.9. Z

3. Timer

3.1. NE555

3.2. Ripple Counter

3.3. 3-to-8 Decoder

3.4. Stop Circuit

4. 8-bit ALU

4.1. Interface

4.1.1. Input A

4.1.2. Input B

4.1.3. Output C

4.1.4. Internal A

4.2. Operations

4.2.1. NOP

4.2.2. XOR

4.2.3. OR

4.2.4. AND

4.2.5. ADD

4.2.6. NOT

4.2.7. SHL

4.2.8. ADC

4.2.9. SUB

4.2.10. NEG

4.2.11. SBB

4.2.12. RCL

4.2.13. SHR

4.2.14. SAR

4.2.15. RCR

4.2.16. MOV8

5. System Buses

5.1. 8-bit Data Bus

5.2. 16-bit Address Bus

5.3. Flags Bus

6. SRAM Memory

7. I/O Ports

7.1. Input Port A

7.2. Input Port B

7.3. Output Port C

7.4. Output Port D