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1. Processor Organization

1.1. Processor Requirements

1.1.1. Fetch Instruction The processor reads an instruction from memory

1.1.2. Interpret instruction The instruction is decoded to determine what action is required

1.1.3. Fetch data The execution of an instruction may require reading data from memory or an I/O module

1.1.4. Process data The execution of an instruction may require performing some arithmetic or logical operation on data

1.1.5. Write data The results of an execution may require writing data to memory or an I/O module

1.2. User-Visible Registers

1.2.1. Enable the machine language programmer to minimize main memory references by optimizing use of registers

1.2.2. Categories General purpose Can be assigned to a variety of functions by the programmer Data May be used only to hold data and cannot be employed in the calculation of an operand address Address May be somewhat general purpose or may be devoted to a particular addressing mode Condition codes Also referred to as flags Bits set by the processor hardware as the result of operations

1.3. Control & Status registers

1.3.1. Used by control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs

2. Register Organization

2.1. Condition Codes

2.1.1. Advantages Because condition codes are set by normal arithmetic & data movement instructions,they should reduce the number of COMPARE and TEST instructions needed. Conditional instructions,such as BRANCH are simplified relative to composite instructions,such as TEST AND BRANCH Condition codes can be saved on the stack during subroutine calls along with other register information

2.1.2. Disadvantages Condition codes add complexity,both to the hardware * software.Condition code bits are often modified in different ways by different instructions,making life more difficult for both the microprogrammer and compiler writer Condition codes are irregular,they are typically not part of the main data path,so they require extra hardware connection In a pipelined implementation,condition codes require special synchronization to avoid conflicts

2.2. Control & Status Registers

2.2.1. Program counter (PC) Contains the address of an instruction to be fetched

2.2.2. Instruction register (IR) Contains the instruction most recently fetched

2.2.3. Memory address register (MAR) Contains the address of a location in memory

2.2.4. Memory buffer register (MBR) Contains a word of data to be written to memory or the word most recently read

2.3. Program Status Word (PSW)

2.3.1. Register or set registers that contain status information Common fields of flags include Sign Zero Carry Equal Overflow Interrupt Enable/Disable Supervisor

3. Instruction Cycle

3.1. Fetch

3.1.1. Read the next instruction from memory into the processor

3.2. Execute

3.2.1. Interpret the opcode and perform the indicated operation

3.3. Interrupt

3.3.1. If interrupts are enabled & an interrupt has occurred,save the current process state and service the interrupt

4. Instruction Pipelining

4.1. Pipelining Strategy

4.1.1. Similar to the use of as assembly line in a manufacturing plant New inputs are accepted at one end before previously accepted inputs appears as outputs at the other end To apply this concept to instruction execution we must recognize that an instruction has a number of stages

4.2. Additional Stages

4.2.1. Fetch instruction (FI) Read the next expected instruction into a buffer

4.2.2. Decode instruction (DI) Determine the opcode and the operand specifies

4.2.3. Calculate operands (CO) Calculate the effective address of each source operand

4.2.4. Fetch operands (FO) Fetch each operand from memory

4.2.5. Execute instruction (EI) Perform the indicated operation and store the result,if any,in the specified destination operand location

4.2.6. Write operand (WO) Store the result in memory

4.3. Pipeline Hazards

4.3.1. Types of Data Hazard Read after write (RAW) or true dependency Write after read (WAR) or antidependency Write after write (WAW) or output dependency

4.3.2. Control Hazard Also known as a branch hazard Occurs when the pipeline makes the wrong decision on a branch prediction Brings instructions into the pipeline that must subsequently be discarded Dealing with Branches Multiple streams Prefetch branch target Loop buffer Branch prediction Delayed branch

5. The x86 Processor Family

5.1. Interrupt Processing

5.1.1. Interrupts

5.1.2. Exceptions

5.1.3. Interrupt vector table

6. The ARM Processor

6.1. Moderate array of uniform registers

6.2. Separate arithmetic logic unit (ALU) & shifter units

6.3. A small number of addressing modes with all load/store addresses determined from registers and instruction fields

6.4. Processor Modes

6.4.1. ARM architecture supports 7 execution modes

6.4.2. Most application programs execute in user mode

6.4.3. Remaining 6 execution modes are referred to as privileged modes

6.4.4. Advantages to defining so many different privileged modes

6.5. Exception Modes

6.5.1. Have full access to system resources and can change modes freely

6.5.2. Entered when specific exceptions occur

6.5.3. Exception modes Supervisor mode Abort mode Undefined mode Fast interrupt mode Interrupt mode

6.5.4. System mode