Chapter 2 : Computer System Structures

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Chapter 2 : Computer System Structures by Mind Map: Chapter 2 : Computer System Structures

1. Computer-System Operation

1.1. A general-purpose computer system consists of one or more CPUs and a number of device controllers.

1.2. Each device controller is in charge of a specific type of device.

1.3. Each device controller has a local buffer.

1.4. The CPU and device controllers can execute concurrently.

1.5. Device controller informs CPU that it has finished its operation by causing an interrupt.

1.6. Interrupt indicates the occurrence of an event from either the hardware or software.

2. Interrupt Handling

2.1. When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a fixed location.

2.2. The fixed location contains the starting address of the interrupt service routine.

2.3. Interrupt vector provides the address of the interrupt service routine for the interrupting device.

2.4. Separate segments of code determine what action should be taken for each type of interrupt.

2.5. The operating system (OS) preserves the state of the CPU by storing registers and the program counter.

2.6. After the interrupt is serviced, the saved return address is loaded into the program counter.

2.7. The interrupted computation resumes.

3. I/O Structure

3.1. Synchronous I/O Structure

3.1.1. After I/O starts, control returns to user program only upon I/O completion.

3.1.2. Wait instruction idles the CPU until the next interrupt occurs.

3.1.3. Wait loop (contention for memory access)

3.1.4. At most one I/O request is outstanding at a time, no simultaneous I/O processing.

3.2. Asynchronous I/O Structure

3.2.1. After I/O starts, control returns to user program without waiting for I/O completion.

3.2.2. System call requests to the operating system to allow user to wait for I/O completion.

3.2.3. Device-status table contains entry for each I/O device indicating its type, address, and state.

3.2.4. Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt.

4. Storage Structure

4.1. Main memory is the only large storage media that the CPU can access directly.

4.2. A volatile storage device will lose its contents when the power is turned off.

4.3. Secondary storage is the extension of main memory that provides non-volatile storage capacity.

4.4. It is capable to hold large quantities of data permanently.

5. Storage Hierarchy

5.1. Storage systems organized in hierarchy.

5.1.1. Speed

5.1.2. Cost

5.1.3. Volatility

5.2. Caching-copying information into faster storage system;main memory can be viewed as a last cache for secondary storage

6. Dual-Mode Operation

6.1. In order to ensure the properexecution of the operating system, the computer system must be able to distinguish between the execution of operating system code and user-defined code .

6.2. Provide hardware support to differentiate between at least two modes of operations .

7. I/O Protection

7.1. All I/O instructions are privileged instructions; user program cannot issue I/O instructions directly

7.1.1. User program must executes a system call to request that the operating system to perform I/O

7.2. Must ensure that a user program could never gain control of the computer in monitor mode (i.e., a user program , as part of its execution,stores a new address in the interrupt vector) .

8. Memory Protection

8.1. The computer system must provide memory protection at least for the interrupt vector and the interrupt service routines.

8.2. In order to have memory protection, two registers are used to determine the range of legal addresses a program may access:

8.2.1. Base register – holds the smallest legal physical memory address.

8.2.2. Limit register – contains the size of the range

8.3. Memory outside the defined range is protected.

9. CPU Protection

9.1. Timer – interrupts computer after specified period to ensure operating system maintains control over CPU

9.1.1. Every time the clock ticks, the counter is decremented.

9.1.2. When timer reaches the value 0, an interrupt occurs

9.2. When timer interrupts, control transfers to the operating system.

9.3. Load-timer is a privileged instruction.